NEO Semiconductor has patented X-NAND technology to accelerate SSD writes by fifteen times and reduce die sizes. Two patents were granted on August 5th.
The company, which was founded in 2016 by CEO Andy Hsu and Engineering VP Ray Tsay, won the Best of Show Award for the most innovative flash memory startup at the Flash Memory Summit 2020. It has developed a way to reduce the page buffer capacity on a NAND chip and parallelize operations, which also increases random and sequential read and write speeds.
Founder and CEO Andy Hsu said: “Technological leaps have driven innovation in the past, so expectations are high that NAND flash memories will become more than an order of magnitude faster. Imagine the possibilities if X-NAND QLC flash memory offers higher bandwidth than traditional SLC flash memory. “
SLC flash (1 bit / cell) is the fastest flash, and every extra bit in a cell means more voltage levels and slower read and write speeds, and a shorter lifespan. X-NAND addresses the speed slowdown but not the life limitations of MLC (2 bits / cell), TLC (3 bits / cell), QLC (4 bits / cell) and PLC (5 bits / cell). Its main feature is that it reduces the page buffer size of a flash die by 94 percent.
This is intended to make it possible to increase the number of chip levels from two or four to 16 or more – up to 64. A level is a collection of NAND cells that are read and written in a single operation, with different level operations taking place in parallel. If sixteen IO operations can be executed in parallel instead of just two or four, the IO speed of the chip increases.
Neo claims that its technology boosts sequential read performance by 27x, sequential write by 15x, and random read and write by 3x. Neo claims that its X-NAND architecture combines QLC density and SLC speed in 3D NAND flash memory and prevents SLC caches from becoming completely full and therefore inoperable. It also reduces the power consumption of the chip, enables its size to be reduced, and does not cause an increase in manufacturing costs. There is no change in NAND cell, array structure, process and technology.
A two-page white paper offers a brief look at the technology, while a 16-page white paper offers a deeper look.
The shorter document explains: “The X-NAND architecture enables a page buffer to perform read and write operations on 16 or more bit lines. This increases the number of levels in the Y direction 16 times or more without increasing the number of total page buffers. This increases the read and write data throughput by a factor of 16. In addition, since the bit line length and the capacity are reduced to 1/16, the random reading speed and the program verification speed are drastically increased. The power consumption of the bit line is also reduced to 1/16. ”
The 16 pager explains: “The program data is sequentially loaded onto 16 bit lines from a page buffer and held in the bit line capacitance to program 16 cells together. This significantly increases the write bandwidth of the page buffers. Since each programming pulse is only 10 μs long, the data can be safely stored in the bit line capacitance without any refresh operations. ”
There’s a lot more of interest to NAND die engineers, and then a table that should be of interest to anyone interested in SSD performance:
It’s a performance estimate, but just look at the numbers. First, sequential read and write operations are amplified more than random I / O. Second, it even speeds up SLC Flash IO 54 times – we specifically asked Neo to confirm this.
SLC speed and NAND endurance
A Neo spokesperson told us, “The reading and writing speed of X-NAND SLC can be increased. By using 16 levels (Y direction), the random read / write speed can be increased by 2x / 1.4x. The sequential read / write data throughput can be increased by 9/5 times. By using 64 levels, the sequential read / write speed can be increased by 30 to 22 times. However, the above data assumes that I / O speed can support this. In fact, X-NAND is so fast that the sequential speed is limited by the I / O speed. “
We also asked if X-NAND could increase stamina. The spokesman said: “By reducing the bit line length and capacitance, the reading process for X-NAND is more reliable than for traditional NAND, which has a very high bit line capacitance load. This enables a tighter and more precisely controlled Vt level for TLC to PLC; so it is possible to improve the endurance cycles. “
The spokesperson added this: “X-NAND has a feature called ‘SLC / (TLC-PLC) Parallel Programming’. With this function, the data can always be written in SLC cells and then shifted in parallel (at the same time) in TLC-PLC cells. The 16-64 level architecture of X-NAND enables a much more uniform “wear leveling” than the conventional four levels. This improves the endurance cycles. “
The company has ten employees and is financed by angel investors. The two U.S. patents have number 11056190 B2 (Methods and Devices for NAND Flash Memory) and 11049579 B2.
To us, it looks like Neo might want to license its technology to NAND manufacturers – Kioxia, Intel, Micron, Samsung, SK Hynix, and Western Digital. That’s a small market in terms of companies.
Neo won the Best of Show Award and received two patents for X-NAND, in addition to its existing 20 patents. That means its technology is reputable and worth a good look.
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